1. Technical Field Invention
The present disclosure relates to a voltage generator of a liquid crystal display (LCD) and, more particularly, to a voltage generator that prevents latch-up.
2. Discussion of Related Art
In a voltage generating circuit, for example, in a complementary metal oxide semiconductor (CMOS) device used generally in a charge pump circuit, a specific state called latch-up exists.
Latch-up indicates that a thyristor operation occurs at a PNPN junction included in a CMOS chip, so that excessive current flows through the chip, thereby causing destruction of the chip. Latch-up occurs when input and output voltages exceed a rated level and thus a large current flows in an internal device or when the voltage of a power terminal exceeds a rated level and, thus, an internal device is in a breakdown state. Although latch-up occurs in an instant, once a chip is in a latch-up state, the latch-up state is continuously maintained until the power is blocked by a thyristor structure, thereby ultimately causing destruction of the chip.
Latch-up that can occur in a voltage generator of a liquid crystal display (LCD) is described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of a conventional liquid crystal display (LCD) including a voltage generator.
Referring to FIG. 1, the LCD 100 includes a timing controller 110, a source driver 120, a voltage generator 130, a gate driver 140, and a liquid crystal panel 150.
The liquid crystal panel 150 includes a plurality of gate lines G1-Gn, a plurality of source lines S1 to Sm crossing the gate lines G1 to Gn, and pixels arranged in regions defined by the gate lines and the source lines.
Each pixel includes a thin film transistor T1, a liquid crystal capacitor CLC, and a storage capacitor CST in which a gate electrode and a source electrode are respectively connected to the gate line and the source line. In such pixels, the gate lines are sequentially selected by the gate driver 140. When a gate-on voltage is applied to the selected gate lines in a pulse form, the thin film transistor T1 of the pixel connected to the gate line is turned on and then a voltage including pixel information is applied to each data line by the source driver 120. The voltage passes through the thin film transistor T1 of the corresponding pixel and is applied to the liquid crystal capacitor CLC and storage capacitor CST. When the liquid crystal and storage capacitors CLC and CST operate, a predetermined display operation is accomplished.
The timing controller 110 receives a current pixel data signal RGB, a vertical synchronization signal V_SYNC, a horizontal synchronization signal H_SYNC, a clock signal MCLK, and a data enable signal DE input from an external device (not shown). When the vertical synchronization signal V_SYNC has, for example, a period of 1/60 of a second, that is, a period of 16.6 [mS], the horizontal synchronization signal H_SYNC has a period of 1/320 of a second, that is, a period of 50 [uS]. Thus, the vertical synchronization signal V_SYNC has a longer period than that of the horizontal synchronization signal H_SYNC.
The timing controller 110 outputs a pixel data signal RGB′ and control signals, in which a data format thereof is converted in order to conform with an interface specification, to the source driver 120. The control signals provided from the timing controller 110 to the source driver 120 include a latch signal TP, a horizontal synchronization start signal STH, and a horizontal clock signal HCLK.
The gate driver 140 responds to the control signals provided from the timing controller 110, that is, a vertical synchronization start signal STV, a gate clock signal GCLK, and an output enable signal OE, and sequentially scans the gate lines G1 to Gn. In this example, the scanning indicates that a gate-on voltage VGH is sequentially applied to the gate lines G1 to Gn and, thus, the pixels of the gate lines G1 to Gn in which the gate-on voltage VGH is applied are in a recordable state.
The voltage generator 130 receives an external power voltage VCI and generates voltages needed to operate the LCD 100, for example, a first voltage (analog power voltage, AVDD), a second voltage (gate-on voltage, VGH), a third voltage (gate-off voltage, VGL), and a fourth voltage (common voltage, VCL). The gate-on voltage VGH and the gate-off voltage VGL are provided to the gate driver 140 and the analog power voltage AVDD is used as an operational voltage of the LCD 100.
When the voltages are generated, latch-up can occur in the conventional voltage generator 130.
FIG. 2 is an equivalent circuit diagram of a PNPN junction of a complementary metal oxide semiconductor (CMOS) device 200.
A charge pump circuit (not illustrated) exists in an internal circuit of the voltage generator 130 illustrated in FIG. 1, and the charge pump circuit generally includes the CMOS device 200 illustrated in FIG. 2.
An internal power voltage VCI1 used in the inside of the voltage generator 130 is generated by using the external power voltage VCI illustrated in FIG. 1. The third voltage VGL is an SI-substrate bias voltage.
The latch-up generation in a boosting mode of the voltage generator 130 will now be described with reference to FIG. 2.
When an emitter voltage of a PNP transistor Q1 is higher than a base voltage, an emitter current flows into a collector terminal. The emitter of the PNP transistor Q1 is connected to the internal power voltage VCI1 through a resistor R1. Because the base of the PNP transistor Q1 is substantially in a floating state before boosting, if the base of the PNP transistor Q1 has an electric potential of 0V that is an arbitrary voltage in an initial stage, an emitter-base voltage is VE=VBE≈0.7V and is forward biased. In this example, the emitter current is IE=(VCI1−VE)/R1.
When a collector voltage of the PNP transistor Q1 is Vc=VGL+IE*R4 and |VGL|<|IE*R4|, Vc is a positive voltage. Thus, an NPN transistor Q2 is turned on. Similarly, an NPN transistor Q3 is also turned on. Because the NPN transistors Q2 and Q3 are turned on, a current path is formed between the second voltage VGH source and a ground voltage VSS source and, thus, excessive current flows. Such an excessive-current state is called latch-up.
As described above, in a boosting mode of the voltage generator 130, when latch-up occurs due to momentary forward biasing, the circuit may be seriously damaged.
In addition, not only in a boosting mode, but also in a normal operation mode of the voltage generator 130, latch-up may occur due to an electric static discharge ESD, a surge voltage, or a faulty operation of a display drive IC DDI.